.. _processorsAccessDoc:

.. index:: single: Port Access Processors

============================
Port Access Processor Blocks
============================

* `Interleave ()`_
* `DeInterleave ()`_
* `GetPort ()`_
* `SetPort ()`_

----

.. index:: single: Interleave()
.. index:: single: Port Access Processors; Interleave
.. _Interleave_PAP:

Interleave ()
=============

::

	Interleave (
		stride:		none
	)

:stride:
	List of port indices to access.

::

	signal Result [2] {}

	# Result is [ 3 , 7 ]
	[ 1 , 2 , 3 , 4 ] >> Add () >> Result;

	# Result is [ 4 , 6 ]
	[ 1 , 2 , 3 , 4 ] >> Interleave ( stride: 2 ) >> Add () >> Result;

----

.. index:: single: DeInterleave()
.. index:: single: Port Access Processors; DeInterleave
.. _DeInterleave_PAP:

DeInterleave ()
===============

::

	DeInterleave (
		stride:		none
	)

:stride:
	List of port indices to access.

----

.. index:: single: GetPort()
.. index:: single: Port Access Processors; GetPort
.. _GetPort_PAP:

GetPort ()
==========

::

	GetPort (
		index:		none
	)

:index:
	Index or indices to access.

----

.. index:: single: SetPort()
.. index:: single: Port Access Processors; SetPort
.. _SetPort_PAP:

SetPort  ()
===========

::

	SetPort  (
		index:		none
	)

:index:
	Index or indices to access.