Index

Symbols

! # &&

>> ||

A

Absolute() AD() Add() Addition ADSR() and And() ArcCos() ArcSin()

ArcTan() Arithmetic Operators as AudioDomain AudioIn AudioOut AudioRate Auxiliary Blocks

B

BandPass() BandReject() Basic Types integer real string BiQuad() Boolean Operators ! && and not or || Boolean Types off on

Built-In Communication Blocks Built-In Constant Blocks Built-In Generators Built-In Module Blocks Built-In Processors

C

Clip() comment Compare() Comparison Processors Equal Greater GreaterOrEqual Less LessOrEqual NotEqual complex Complex Generators CxOscillator Complex Processors Configuration Descriptor File constant ControlDomain ControlIn ControlOut

ControlRate Core Blocks Cos() Counter() CxAdd() CxImag() CxMagnitude() CxMultiply() CxOscillator () CxPhase() CxReal()

D

DeInterleave() dictionary DigitalIn

DigitalOut Divide()

E

Envelope Processors AD ADSR Envelope Envelope() Equal()

Example A Vocoder Amplitude Modulation Blocks, Ports, and Properties Bypassing with Switches Complex Sinusoids Control Flow with Select() Control with Presets FIR Filter and Module Feedback and Processor Modules Frequency Domain Frequency Modulation Granular Synthesis Latching a Switch Merge Oscillators and Generator Modules Processors, [1], [2] Propagating Rates: streamRate Random Numbers Reactions Recursion Remote Control Ring Modulation SampleHold Block Shorthand Declarations Sine Table Generator Slider The Table Module Block Exp()

F

Files Configuration Descriptor File Hardware Descriptor File Platform Descriptor File Filter Processors BandPass BandReject BiQuad HighPass HighShelf LowPass LowShelf

FixedDelay() from

G

Generators Counter ImpulseTrain Oscillator PulseTrain Random UnitStep GetPort() Getting Started

Greater() GreaterOrEqual()

H

Hardware Descriptor File HighPass()

HighShelf() hybrid

I

import ImpulseTrain() in

integer Interleave() Invert()

K

Keywords as from import in none off on out streamDomain streamRate use version with

L

Less() LessOrEqual() Level() Ln() Log()

Logic Processors Or LogicProcessors And LowPass() LowShelf()

M

M_E M_PI Map() MasterReset Mathematical Processors Absolute Add ArcCos ArcSin ArcTan Cos CxAdd CxImag CxMagnitude CxMultiply CxPhase CxReal Divide Exp Ln Log Maximum Minimum Modulo Multiply Power Sin SquareRoot Subtract Tan Maximum() midi MidiIn

MidiOut Minimum() Mix() Modular Blocks module Modulo() Multiplication Multiply()

N

none not

NotEqual()

O

off on OnChange() Operator Precedence Operators or

Or() osc Oscillator() OscIn OscOut out

P

Pan() Platform Descriptor File Port Access Processors DeInterleave GetPort Interleave SetPort Port Connections Boolean Output - Integer Input Boolean Output - Real Input Integer Output - Boolean Input Integer Output - Real Input Real Output - Boolean Input Real Output - Integer Input Port Directions Input Output

Port Types Constant Boolean (CBP) Constant Integer (CIP) Constant Real (CRP) Constant String (CSP) Stream Boolean (SBP) Stream Integer (SIP) Stream Real (SRP) Stream String (SSP) Ports Power() PulseTrain()

R

Random() reaction real

Real Constants M_E M_PI Rectify() Round()

S

serial SerialIn SerialOut SetPort() signal Signal Conditioning Processors Clip Compare FixedDelay Invert Level Map Mix OnChange Pan Rectify Round Sin() SquareRoot()

Stream Expression Stream Operator streamDomain streamRate string Subtract() switch Syntax Newline Semicolon Tab White Space

T

Tan() trigger

Types

U

UnitStep()

use

V

variable

version

W

with